This report separates two ideas that are often collapsed into one trade. CoPoS is a panel-level advanced-packaging path. Glass core substrate is a materials and process shift that may be used in CoPoS, advanced CoWoS, EMIB/Foveros, or other chiplet packages.
The key conclusion is not that glass replaces CoWoS tomorrow. The more investable frame is that 2026-2027 is a qualification and equipment-order window, 2028-2029 is an initial high-end ramp window, and broader glass-core adoption is likely a post-2030 question.
For public-equity triage, the cleaner work is to rank beneficiaries by process bottleneck and qualification proof: glass-core suppliers, TGV/process equipment, high-end IC substrate makers, and the foundry or OSAT owners of the packaging flow.
CoPoS / Glass Core Substrate / AI Packaging
This is not an immediate CoWoS replacement. It is a new constraint stack: area, yield, materials and tools.
CoPoS targets panel-level scale for very large AI packages. Glass core substrates target the material limits of organic cores: flatness, thermal expansion, high-frequency loss and large-panel stability. Related, but not identical.
What CoPoS is
Chip-on-Panel-on-Substrate moves part of the package flow toward rectangular panels to gain larger package area and potential cost efficiency. It is primarily a process and form-factor shift.
What glass core is
Glass core replaces or supplements the organic core with a flatter, lower-loss, lower-CTE material that can support TGV and finer large-area routing.
1. AI chiplet demand
Larger GPU/ASIC packages and more HBM stacks raise the package-size problem.
2. CoWoS keeps scaling
TSMC still argues wafer-level packaging is more mature and has runway.
3. Panel-level option
CoPoS becomes an option when area and cost pressure rise further.
4. Glass-core evaluation
Glass offers flatness, CTE control and low-loss routing for larger packages.
5. Manufacturing gates
TGV, metallization, breakage, inspection and qualification decide economics.
Package stack: the chip does not simply sit on raw glass
| Path | Advantages | Drawbacks / bottlenecks | Investment meaning |
|---|---|---|---|
| Organic ABF substrate | Mature ecosystem and current AI/CPU/GPU substrate base. | Warpage, CTE mismatch, line-space pressure, loss and layer-count complexity rise with size. | Incumbents still benefit first; glass is not an instant replacement. |
| Silicon interposer / CoWoS | Highest proven interconnect density and best current HBM integration. | Area, cost, capacity and economics become harder at ultra-large sizes. | TSM remains the main line; CoPoS is an option, not the 2026 default. |
| EMIB / embedded bridge | Local high-density connection without a full silicon interposer. | External foundry traction and ecosystem scale are still questions. | INTC has real technology optionality but a noisy stock thesis. |
| Fan-out / CoPoS | Panel form factor may allow larger packages and better area economics. | Panel lithography, overlay, RDL uniformity, inspection and tools are less mature. | Watch validation and tool orders before underwriting revenue. |
| Glass core substrate | Flat, lower CTE, lower high-frequency loss, large-panel compatible, TGV-capable. | Brittleness, TGV, metallization, copper fill, build-up integration, reliability and cost. | Purest names are SKC/Absolics, Samsung Electro-Mechanics, AGC/Corning and LPKF. |
Why glass matters
- Better flatness for finer routing.
- Lower thermal expansion versus organic cores.
- Low electrical loss at high frequencies.
- Panel form factor for future package scaling.
Why it is hard
- Thin large glass is fragile.
- TGV drilling and metallization are process bottlenecks.
- Panel-level tools trail wafer-level tools.
- Qualification cycles are long and yield losses are expensive.
What to verify
- Named customer qualification.
- Repeat orders for glass-processing equipment.
- Public TGV, warpage and reliability data.
- Sample-to-HVM conversion at substrate suppliers.
| Priority | Company / layer | Purity | Why it surfaced | First rejection |
|---|---|---|---|---|
| A | 011790.KS SKC / Absolics | High | One of the cleanest glass-substrate exposure paths; NIST/CHIPS and Georgia capacity support the proof path. | Subsidiary transparency and concentrated execution risk. |
| A | 009150.KS Samsung Electro-Mechanics | Medium-high | Package-substrate and MLCC base, glass pilot line, 2027 goal and Sumitomo glass-core JV. | Early revenue mix is small and customer proof is incomplete. |
| A | 4062.T Ibiden | Medium | Incumbent high-end IC substrate winner with a JPY500B AI/server substrate capex plan. | Less pure glass exposure; heavy capex and cycle risk. |
| B | LPK.DE LPKF | Medium-high | LIDE/TGV tools are a pick-and-shovel route into glass processing. | Need repeat production orders, not only R&D tools. |
| B | 5201.T AGC / GLW Corning | Medium | Precision glass, TGV, carrier glass and large-panel know-how. | Group-level exposure may be diluted by non-packaging businesses. |
| B | TSM / INTC / AMKR | Low-medium | Route owners and OSAT beneficiaries, but not pure glass trades. | Stock drivers are broader than glass substrates. |
| C | Innolux / AUO | Event-driven | Panel manufacturing know-how may matter if CoPoS uses local panel partners. | Very early validation trade; manufacturing know-how is not final package yield. |
This is not everything yet. It is enough to answer what the technology is, where the bottlenecks sit, and which exposures are cleaner. It is not enough by itself to decide whether to buy now, how large to size, or which instrument to use. The missing layers are live valuation, customer-order proof, and trade execution.
| Decision layer | What this report supports | What is still missing | When to update |
|---|---|---|---|
| Understanding and screening | Usable: the CoPoS versus glass-core boundary, pros and cons, bottlenecks, timeline and purity map are enough for first-pass screening. | No major concept gap, but industry validation must be refreshed. | Whenever TSMC, Intel, Samsung Electro-Mechanics, Ibiden or SKC/Absolics discloses packaging or substrate progress. |
| Valuation and sizing | Not directly usable: this report does not include live prices, market caps, EV/Sales, EV/EBITDA, revenue sensitivity or depreciation pressure. | Company-level base/bull/bear revenue contribution, margin, capex, depreciation and valuation sensitivity. | Before any real position build or add, refresh with the latest filings, prices and guidance. |
| Catalyst verification | Usable as a checklist: customer qualification, repeat tool orders, pilot-to-HVM schedule and package specifications are the key proofs. | A dated event calendar, evidence hierarchy and falsification signals. | During the 2026H2-2027 qualification window, update after earnings calls, tool orders and customer qualification news. |
| Trade expression | Not directly usable: the report ranks purity, but does not define option liquidity, stops, entries or portfolio weights. | Separate U.S.-listed proxies, Japan/Korea/Taiwan direct exposure, ETF baskets and event trades. | Once the tradable market is fixed, build a dedicated execution plan. |
Zero-to-one investment conclusion: treat CoPoS and glass core as a qualification-cycle theme, not a near-term revenue boom. The first research queue is SKC/Absolics, Samsung Electro-Mechanics and Ibiden; U.S.-listed proxies are lower-purity GLW, AMKR, TSM and INTC. The real proof is customer qualification, repeat tool orders, pilot-to-HVM timing and public package specifications.