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Articles
Build notes, thinking notes, field records, and DYOR research share one filterable Articles board; DYOR still keeps dedicated visual report pages.
All articles · Showing 31-36 of 43
POET / MXL / HIMX: three layers of AI interconnect optionality
POET, MXL and HIMX can all be mapped to AI interconnect, optics, CPO or edge AI, but the first-principles layers are different. POET is a manufacturing-platform option: can Optical Interposer / EOI move optical-engine production closer to wafer-scale integration? MXL is the signal-chain layer: optical modules and AI data-center links need PAM4 DSPs, TIAs and retimers. HIMX is a display and ultra-low-power sensing company with AR, WiseEye and CPO optionality through FOCI.
I Put the /goal Lesson Back into Superloop
This update did not add more agents. It added recoverable runtime context: what the next round should do, why it should do it, and what counts as done.
Cerebras WSE: The Wafer-Scale Answer to AI Inference
Cerebras's Wafer-Scale Engine (WSE) treats an entire 12-inch silicon wafer as a single chip, rather than slicing it into hundreds of small GPUs and wiring them back together like NVIDIA does.
U.S. optical earnings map: where the AI interconnect bottleneck sits
From first principles, AI optics is not a theme label. As AI clusters grow denser, the cost of moving data across GPUs, racks, data halls and data centers rises sharply. GPUs are the compute bottleneck; optical interconnect is the data-movement bottleneck.
Big Four AI CapEx receiver chain
This report uses the 2026-04-29 earnings cycle and later capex summaries as the base: Amazon around $200B, Microsoft around $190B, Alphabet/Google at a $185B midpoint, and Meta at the $135B midpoint of its $125B-$145B range.
1.6T optical order chain
The key question for 1.6T is not whether demos are exciting, but whether the chain has moved from sampling to repeatable volume logic.